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51612hkpc /31710hkim 20100223-s00003,s00005,s00006/82008hkim no.a0964-1/43 http://onsemi.com semiconductor components industries, llc, 2013 july, 2013 LC75818PT overview the LC75818PT is 1/8 to 1/10 duty dot matrix lcd display controllers/drivers that suppor t the display of characters, numbers, and symbols. in addition to generating dot matrix lcd drive signals based on data transferred serially from a microcontroller, the LC75818PT also provide on-chip character display rom and ram to allow display systems to be implemented easily. these products also provide up to 4 general-purpose output ports and incorporate a key scan circuit that accepts input from up to 30 keys to reduce printed circuit board wiring. features ? key input function for up to 30 keys (a key scan is performed only when a key is pressed.) ? controls and drives a 5 7, 5 8, or 5 9 dot matrix lcd. ? supports accessory display segment drive (up to 80 segments) ? display technique: 1/8 duty 1/4 bias drive (5 7 dots) 1/9 duty 1/4 bias drive (5 8 dots) 1/10 duty 1/4 bias drive (5 9 dots) ? display digits: 16 digits 1 line (5 7 dots, 5 8 dots, 5 9 dots) ? display control memory cgrom: 240 characters (5 7, 5 8, or 5 9 dots) cgram: 16 characters (5 7, 5 8, or 5 9 dots) adram: 16 5 bits dcram: 64 8 bits ? instruction function display on/off control display shift function ? sleep mode can be used to reduce current drain. ? built-in display contrast adjustment circuit ? the frame frequency of the common and segment output waveforms can be controlled by instructions. ? serial data i/o supports ccb format co mmunication with the system controller. ? independent lcd driver block power supply v lcd ? a voltage detection type reset circuit is provided to initialize the ic and prevent incorrect display. ? the inh pin is provided. this pin turns off the display, disables key scanning, and forces the general-purpose output ports to the low level. ? rc oscillator circuit ordering number : ena0964b cmos ic 1/8 to 1/10 duty dot matrix lcd display controllers/drivers wi th key input function ? ccb is on semiconductor? ?s original format. all addresses are managed by on semiconductor? for this format. ? ccb is a registered trademark of semiconductor components industries, llc.
LC75818PT no.a0964-2/43 specifications absolute maximum ratings at ta = 25 c, v ss = 0v parameter symbol conditions ratings unit v dd max v dd -0.3 to +4.2 maximum supply voltage v lcd max v lcd -0.3 to +11.0 v ce, cl, di, inh -0.3 to +4.2 v in 1 ce, cl, di, inh v dd =2.7 to 3.6v -0.3 to +6.5 v in 2 osc, ki1 to ki5, test -0.3 to v dd +0.3 input voltage v in 3 v lcd 1, v lcd 2, v lcd 3, v lcd 4 -0.3 to v lcd +0.3 v v out 1 do -0.3 to +6.5 v out 2 osc, ks1 to ks6, p1 to p4 -0.3 to v dd +0.3 output voltage v out 3 v lcd 0, s1 to s80, com1 to com10 -0.3 to v lcd +0.3 v i out 1 s1 to s80 300 a i out 2 com1 to com10 3 i out 3 ks1 to ks6 1 output current i out 4 p1 to p4 5 ma allowable power dissipation pd max ta=85 c 200 mw operating temperature topr -40 to +85 c storage temperature tstg -55 to +125 c allowable operating range at ta = -40 c to +85 c, v ss = 0v ratings parameter symbol conditions min typ max unit v dd v dd 2.7 3.6 v lcd when the display contrast adjustment circuit is used. 7.0 10.0 supply voltage v lcd v lcd when the display contrast adjustment circuit is not used. 4.5 10.0 v output voltage v lcd 0 v lcd 0 v lcd 4 +4.5 v lcd v v lcd 1 v lcd 1 3/4 (v lcd 0 - v lcd 4) v lcd 0 v lcd 2 v lcd 2 2/4 (v lcd 0 - v lcd 4) v lcd 0 v lcd 3 v lcd 3 1/4 (v lcd 0 - v lcd 4) v lcd 0 input voltage v lcd 4 v lcd 4 0 1.5 v continued on next page. stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended oper ating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliabili ty.
LC75818PT no.a0964-3/43 continued from preceding page. ratings parameter symbol conditions min typ max unit ce, cl, di, inh 0.8v dd 3.6 v ih 1 ce, cl, di, inh v dd =2.7 to 3.6v 0.8v dd 5.5 v ih 2 osc external clock operating mode 0.8v dd v dd input high level voltage v ih 3 ki1 to ki5 0.6v dd v dd v v il 1 ce, cl, di, inh , ki1 to ki5 0 0.2v dd input low level voltage v il 2 osc external clock operating mode 0 0.2v dd v output pull-up voltage v oup do 0 5.5v recommended external resistor for rc oscillation rosc osc rc oscillator operating mode 10 k recommended external capacitor for rc oscillation cosc osc rc oscillator operating mode 470 pf guaranteed range of rc oscillation fosc osc rc oscillator operating mode 150 300 600 khz external clock operating frequency f ck osc external clock operating mode [figure 4] 100 300 600 khz external clock duty cycle d ck osc external clock operating mode [figure 4] 30 50 70 % data setup time tds cl, di [figure 2],[figure 3] 160 ns data hold time tdh cl, di [figure 2],[figure 3] 160 ns ce wait time tcp ce, cl [figure 2],[figure 3] 160 ns ce setup time tcs ce, cl [figure 2],[figure 3] 160 ns ce hold time tch ce, cl [figure 2],[figure 3] 160 ns high level clock pulse width t h cl [figure 2],[figure 3] 160 ns low level clock pulse width t l cl [figure 2],[figure 3] 160 ns do output delay time tdc do r pu =4.7k c l =10pf *1 [figure 2],[figure 3] 1.5 s do rise time tdr do r pu =4.7k c l =10pf *1 [figure 2],[figure 3] 1.5 s note: * 1. since the do pin is an open-drain output, these times depend on the values of the pull-up resistor r pu and the load capacitance c l . electrical characteristics for the allowable operating ranges ratings parameter symbol pins conditions min typ max unit hysteresis v h ce, cl, di, inh , ki1 to ki5 0.1v dd v power-down detection voltage v det 2.0 2.2 2.4 v v i =3.6v 5.0 i ih 1 ce, cl, di, inh v i =5.5v v dd =2.7 to 3.6v 5.0 input high level current i ih 2 osc v i =v dd external clock operating mode 5.0 a i il 1 ce, cl, di, inh v i =0v -5.0 input low level current i il 2 osc v i =0v external clock operating mode -5.0 a input floating voltage v if ki1 to ki5 0.05v dd v pull-down resistance r pd ki1 to ki5 v dd =3.3v 50 100 250 k output off leakage current i offh do v o =5.5v 6.0 a v oh 1 s1 to s80 i o =-20 a v lcd o-0.6 v oh 2 com1 to com10 i o =-100 a v lcd o-0.6 v oh 3 ks1 to ks6 i o =-250 a v dd -0.8 v dd -0.4 v dd -0.1 output high level voltage v oh 4 p1 to p4 i o =-1ma v dd -0.9 v v ol 1 s1 to s80 i o =20 a v lcd 4+0.6 v ol 2 com1 to com10 i o =100 a v lcd 4+0.6 v ol 3 ks1 to ks6 i o =12.5 a 0.1 0.4 1.2 v ol 4 p1 to p4 i o =1ma 0.9 output low level voltage v ol 5 do i o =1ma 0.1 0.3 v continued on next page.
LC75818PT no.a0964-4/43 continued from preceding page. ratings parameter symbol pins conditions min typ max unit v mid 1 s1 to s80 i o = 20 a 2/4 (v lcd 0 -v lcd 4) -0.6 2/4 (v lcd 0 -v lcd 4) +0.6 v mid 2 com1 to com10 i o = 100 a 3/4 (v lcd 0 -v lcd 4) -0.6 3/4 (v lcd 0 -v lcd 4) +0.6 output middle level voltage *2 v mid 3 com1 to com10 i o = 100 a 1/4 (v lcd 0 -v lcd 4) -0.6 1/4 (v lcd 0 -v lcd 4) +0.6 v oscillator frequency fosc osc rosc=10k cosc=470pf 210 300 390 khz i dd 1 v dd sleep mode 100 i dd 2 v dd v dd =3.6v output open fosc=300khz 500 1000 i lcd 1 v lcd sleep mode 15 i lcd 2 v lcd v lcd =10.0v output open fosc=300khz when the display contrast adjustment circuit is used. 450 900 current drain i lcd 3 v lcd v lcd =10.0v output open fosc=300khz when the display contrast adjustment circuit is not used. 200 400 a note: *2. excluding the bias voltage generation divider resistor built into the v lcd 0, v lcd 1, v lcd 2, v lcd 3, and v lcd 4. (see figure 1.) excluding these resistors to the common and segment drivers [figure 1] v lcd v lcd 3 v lcd 4 v lcd 2 v lcd 0 v lcd 1 contrast adjuster
LC75818PT no.a0964-5/43 (1) when cl is stopped at the low level (2) when cl is stopped at the high level [figure 3] (3) osc pin clock timing in external clock operating mode tdh 50% v ih 1 v ih 1 v il 1 v il 1 v ih 1 v il 1 tdr tdc tch tcs tcp tds cl t [figure 2] 50% v ih 1 tdh v ih 1 v il 1 v ih 1 v il 1 tdr tdc tch tcs tcp tds cl t [figure 4] v ih 2 v il 2 osc t ck l t ck h f ck = [khz] d ck = t ck h t ck h + t ck l 100[%] 50% 1 t ck h + t ck l
LC75818PT no.a0964-6/43 package dimensions unit : mm (typ) 3257a pin assignments sanyo : tqfp120(14x14) 0.125 120 0.15 0.4 (1.2) 1 14.0 16.0 14.0 16.0 1.2max 0.1 (1.0) 0.5 LC75818PT (tqfp120) 61 90 60 91 31 120 30 1 s5 s11 s4 s3 s2 s1 s10 s9 s8 s7 s6 s16 s22 s15 s14 s13 s12 s21 s20 s19 s18 s17 s25 s24 s23 s27 s26 s30 s29 s28 s40 s39 s38 s37 s36 s34 s35 s32 s33 s31 s45 s44 s43 s42 s41 s50 s49 s48 s47 s46 s55 s54 s53 s52 s51 s60 s59 s58 s57 s56 s74 s75 s65 s61 s62 s63 s64 s66 s67 s68 s69 s70 s71 s72 s73 s76 s77 s78 s79 s80 com10 com9 com8 com7 com6 com1 com5 com4 com3 com2 ki1 ki3 ki2 ki4 ks6 ki5 v dd v lcd v lcd 1 v lcd 0 v lcd 3 v lcd 2 v lcd 4 test v ss p2 p1 p3 osc p4 inh ce do cl di ks2 ks4 ks3 ks5 ks1 top view
LC75818PT no.a0964-7/43 block diagram s80 adram 80 bits cgram 5 9 16 bits v det clock generator contrast adjuster timing generator address register instruction register common driver instruction decoder address counter dcram 64 8 bits cgrom 5 9 240 bits s h i f t r e g i s t e r l a t c h s e g m e n t d r i v e r osc do di ks1 ks2 ks3 ks4 ks5 ks6 ce ki1 ki2 ki3 ki4 ki5 cl s1 s78 com10 com1 s79 key buffer ccb interface key scan v dd v lcd 4 v lcd 3 v lcd 2 v lcd 1 v lcd v lcd 0 v ss test inh p2 p1 p4 p3 general port
LC75818PT no.a0964-8/43 pin functions pin pin no. function active i/o handling when unused s1 to s80 1 to 80 segment driver outputs. - o open com1 to com10 90 to 81 common driver outputs. - o open ks1 to ks6 91 to 96 key scan outputs. although normal key scan timing lines require diodes to be inserted in the timing lines to prevent shorts, since these outputs are unbalanced cm os transistor outputs, these outputs will not be damaged by shorting when these outputs are used to form a key matrix. - o open ki1 to ki5 97 to 101 key scan inputs. these pins have built-in pull-down resistors. h i gnd p1 to p4 102 to 105 general-purpose outputs. p4 can be used as a clock output port with the "set key scan output port/general-purpose output port state" instruction. - o open osc 115 oscillator connections. an oscillator circuit is formed by connecting an external resistor and capacitor to this pin. this pin can also be used as the external clock input pin with the "set display technique" instruction. - i/o v dd ce 118 h i cl 119 i di 120 - i gnd do 117 serial data interface connections to the controller. note that do, being an open-drain output, requires a pull-up resistor. ce: chip enable cl: synchronization clock di: transfer data do: output data - o open inh 116 input that turns the display off, disables key scanning, and forces the general-purpose output ports low. ? when inh is low (v ss ): ? display off s1 to s80=?l? (v lcd 4) com1 to com10=?l? (v lcd 4) ? general-purpose output ports p1 to p4=low (v ss ) ? key scanning disabled: ks1 to ks6=low (v ss ) ? all the key data is reset to low. ? when inh is high (v dd ): ? display on ? the state of the pins as key scan output pins or general-purpose output ports can be set with the "set key scan output port/general-purpose output port state" instruction. ? key scanning is enabled. however, serial data can be transferred when the inh pin is low. l i v dd test 114 this pin must be connected to ground. - i - v lcd 0 108 lcd drive 4/4 bias voltage (high level) supply pin. the level on this pin can be changed by the displa y contrast adjustment circuit. however, (v lcd 0 - v lcd 4) must be greater than or equal to 4.5v. also, external power must not be applied to this pin since the pin circuit includes the display contrast adjustment circuit. - o open v lcd 1 109 lcd drive 3/4 bias voltage (middl e level) supply pin. this pin can be used to supply the 3/4 (v lcd 0 - v lcd 4) voltage level externally. - i open v lcd 2 110 lcd drive 2/4 bias voltage (middl e level) supply pin. this pin can be used to supply the 2/4 (v lcd 0 - v lcd 4) voltage level externally. - i open continued on next page.
LC75818PT no.a0964-9/43 continued from preceding page. pin pin no. function active i/o handling when unused v lcd 3 111 lcd drive 1/4 bias voltage (middl e level) supply pin. this pin can be used to supply the 1/4 (v lcd 0 - v lcd 4) voltage level externally. - i open v lcd 4 112 lcd drive 0/4 bias voltage (low level) supply pin. fine adjustment of the display cont rast can be implemented by connecting an external variable resistor to this pin. however, (v lcd 0 - v lcd 4) must be greater than or equal to 4.5v, and v lcd 4 must be in the range 0v to 1.5v, inclusive. - i gnd v dd 106 logic block power supply connection. provide a voltage of between 2.7to 3.6v. - - - v lcd 107 lcd driver block power supply connection. provide a voltage of between 7.0 to 10.0v when the display contrast adjustment circuit is used and provide a voltage of between 4.5 to 10.0v when the circuit is not used. - - - v ss 113 power supply connection. connect to ground. - - - block functions ? ac (address counter) ac is a counter that provides the addresses used for dcram and adram. the address is automatically modified internally, and the lcd display state is retained. ? dcram (data control ram) dcram is ram that is used to store display data expres sed as 8-bit character codes. (these character codes are converted to 5 7, 5 8, or 5 9 dot matrix character patterns using cg rom or cgram.) dcram has a capacity of 64 8 bits, and can hold 64 characters. the table below lists the corresponde nce between the 6-bit dcram address loaded into ac and the display position on the lcd panel. ? when the dcram address loaded into ac is 00h. display digit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 dcram address (hexadecimal) 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f however, when the display shift is performed by specifying mdata, the dcram address shifts as shown below. display digit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 dcram address (hexadecimal) 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 (shift left) display digit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 dcram address (hexadecimal) 3f 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e (shift right) note: *3. the dcram address is expressed in hexadecimal. dcram address da0 da1 da2 da3 da4 da5 hexadecimal hexadecimal example: when the dcram address is 2eh. da0 da1 da2 da3 da4 da5 0 1 1 1 0 1 most significant bit msb least significant bit lsb
LC75818PT no.a0964-10/43 ? adram (additional data ram) adram is ram that is used to store the ad ata display data. adram has a capacity of 16 5 bits, and the stored display data is displayed directly without the use of cgrom or cgram. the table below lists the correspondence between the 4-bit adram address loaded into ac and the display position on the lcd panel. ? when the adram address loaded into ac is 0h. (number of digit displayed: 16) display digit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 adram address (hexadecimal) 0 1 2 3 4 5 6 7 8 9 a b c d e f however, when the display shift is performed by specifying adata, the adram address shifts as shown below. display digit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 adram address (hexadecimal) 1 2 3 4 5 6 7 8 9 a b c d e f 0 (shift left) display digit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 adram address (hexadecimal) f 0 1 2 3 4 5 6 7 8 9 a b c d e (shift right) note: *4. the adram address is expressed in hexadecimal. adram address ra0 ra1 ra2 ra3 hexadecimal example: when the adram address is ah. ra0 ra1 ra2 ra3 0 1 0 1 ? cgrom (character generator rom) cgrom is rom that is used to generate the 240 kinds of 5 7, 5 8, or 5 9 dot matrix character patterns from the 8-bit character codes. cgrom has a capacity of 240 45 bits. when a character co de is written to dcram, the character pattern stored in cgrom corr esponding to the character code is displayed at the position on the lcd corresponding to the dcram address loaded into ac. ? cgram (character generator ram) cgram is ram to which user programs can freely write arbitr ary character patterns. up to 16 kinds of 5 7, 5 8, or 5 9 dot matrix character patterns can be stored. cgram has a capacity of 16 45 bits. most significant bit msb least significant bit l s b
LC75818PT no.a0964-11/43 serial data input (1) when cl is stopped at the low level (2) when cl is stopped at the high level ? b0 to b3, a0 to a3: ccb address 42h ? d0 to d63: instruction data the data is acquired on the rising edge of the cl signal and latched on the falling edge of the ce signal. when transferring instruction data from the microcontroller, applica tions must assure that the time from the transfer of one set of instruction data until the next instruction data transfer is significantly longer than the instruction execution time. instruction data (up to 64 bits) d63 d62 d4 d3 d2 0 0 0 0 1 0 1 0 d0 d1 ce di do cl a3 a2 a1 a0 b3 b2 b1 b0 instruction data (up to 64 bits) d63 d62 d4 d3 d2 1 0 0 0 0 0 1 0 d0 d1 ce cl di do a3 a2 a1 a0 b3 b2 b1 b0
LC75818PT no.a0964-12/43 notes: * 5. be sure to execute the "set display t echnique" instruction first after power-on (v det -based system reset). note that th e execution time of this first instruction is 108 s (fosc=300khz, f ck =300khz). * 6. the data format differs when the ?dcram data write? instruction is executed in the increment mode (im = 1). (see detailed instruction descriptions .) * 7. the data format differs when the ?adram data write? instruction is executed in the increment mode (im = 1). (see detailed instruction descriptions.) * 8. the execution times listed here apply when fosc=300khz, f ck =300khz. the execution times differ when the oscillator frequency fosc or the external clock frequency f ck differs. example: when fosc = 210khz, f ck = 210khz 27 s = 39 s, 108 s = 155 s * 9.when the sleep mode (sp = 1) is set, the execution time is 27 s (when fosc = 300khz, f ck = 300khz). 300 210 300 210 instruction table set ac address display shift display on/off control set display technique *5 cd1 cd2?cd40 ad1 ad2 ad3 ad4 ad5 x x x ac0 ac1 ac2 ac3 ac4 ac5 ac6 ac7 ca0 ca1 ca2 ca3 ca4 ca5 ca6 ca7 ra0 ra1 ra2 ra3 x x x x da0 da1 da2 da3 da4 da5 x x da0 da1 da2 da3 da4 da5 x x kc1 kc2 kc3 kc4 kc5 kc6 pc40 pc41 ct0 ct1 ct2 ct3 x x x x dg9 dg10 dg11 dg12 dg13 dg14 dg15 dg16 dg1 dg2 dg3 dg4 dg5 dg6 dg7 dg8 cd41 cd42 cd43 cd44 cd45 x x x execution time *8 d60 d61 d62 d63 0 s 0 s 27 s 27 s 27 s 27 s 27 s 0 s/27 s *9 0 1 1 0 0 1 0 1 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 1 1 0 0 1 1 0 0 0 im x x x ra0 ra1 ra2 ra3 m a r/l x m a sc sp dt1 dt2 fc oc ctc x x x d56 d57 d58 d59 x x x x pc1 pc2 pc3 x im x x x d48 d49 d50 d51 d52 d53 d54 d55 d40 d41 d42 d43 d44 d45 d46 d47 d0 d1... d39 instruction dcram data write *6 adram data write *7 cgram data write set key scan output port/ general-purpose output port state set display contrast x: don ? t care 0 s/108 s *5
LC75818PT no.a0964-13/43 detailed instruction descriptions ? set display technique ... (display technique) code d56 d57 d58 d59 d60 d61 d62 d63 dt1 dt2 fc 0c 0 0 0 1 x: don?t care dt1, dt2: sets the display technique output pins dt1 dt2 display technique com9 com10 0 0 1/8 duty, 1/4 bias drive v lcd 4 level v lcd 4 level 1 0 1/9 duty, 1/4 bias drive com9 v lcd 4 level 0 1 1/10 duty, 1/4 bias drive com9 com10 fc: sets the frame frequency of the common and segment output waveforms frame frequency fc 1/8 duty, 1/4 bias drive f8[hz] 1/9 duty, 1/4 bias drive f9[hz] 1/10 duty, 1/4 bias drive f10[hz] 0 fosc/3072, f ck /3072 fosc/3456, f ck /3456 fosc/3840, f ck /3840 1 fosc/1536, f ck /1536 fosc/1728, f ck /1728 fosc/1920, f ck /1920 oc: sets the rc oscillator operating mode and external clock operating mode. oc osc pin function 0 rc oscillator operating mode 1 external clock operating mode note: *11. when selecting the rc oscillator operating mode, be sure to connect an external resistor rosc and an external capacitor cosc to the osc pin. ? display on/off control ... (display on/off control) code d40 d41 d42 d43 d44 d45 d46 d47 d48 d49 d50 d51 d52 d53 d54 d55 d56 d57 d58 d59 d60 d61 d62 d63 dg1 dg2 dg3 dg4 dg5 dg6 dg7 dg8 dg9 dg10 dg11 dg12 dg13 dg14 dg15 dg16 m a sc sp 0 0 1 0 x: don?t care m, a: specifies the data to be turned on or off m a display operating state 0 0 both mdata and adata are turned off (the display is forcibly turned off regardless of the dg1 to dg16 data.) 0 1 only adata is turned on (the adata of display digits specified by the dg1 to dg16 data are turned on.) 1 0 only mdata is turned on (the mdata of display digi ts specified by the dg1 to dg16 data are turned on.) 1 1 both mdata and adata are turned on (the mdata and adata of displa y digits specified by the dg1 to dg16 data are turned on.) note: *12. mdata, adata 5 7 dot matrix display 5 8 dot matrix display 5 9 dot matrix display note: be sure to execute the "set display technique" instruction first after power-on (v det -based system reset). note: *10. comn (n=9,10): common output ----- adata --- mdata ----- adata --- mdata ----- adata --- mdata
LC75818PT no.a0964-14/43 dg1 to dg16: specifies the display digit display digit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 display digit data dg1 dg2 dg3 dg4 dg5 dg6 dg7 dg8 dg9 dg10 dg11 dg12 dg13 dg14 dg15 dg16 for example, if dg1 to dg7 are 1, and dg8 to dg16 are 0, then display digits 1 to 7 will be turned on, and display digits 8 to 16 will be turned off (blanked). sc: controls the common and segment output pins sc common and segment output pin states 0 output of lcd drive waveforms 1 fixed at the v lcd 4 level (all segments off) note: *13. when sc is 1, the s1 to s80 and com1 to com10 output pins are set to the v lcd 4 level, regardless of the m, a, and dg1 to dg16 data. sp: controls the normal mode and sleep mode sp mode 0 normal mode 1 sleep mode the common and segment pins go to the v lcd 4 level and the oscillator on the osc pin is stopped (although it operates during key scan operations) in rc oscillator operating mode (oc="0") and reception of the external clock is stopped (external clock is received during key scan operations) in external clock operating mode (oc="1"), to reduce current drain. although the "display on/off cont rol", "set display contrast" and "set key scan output port/general-purpose output port state" (disallowed to set the clock output at the p4 pin) instructions c an be executed in this mode, app lications must return the ic t o normal mode to execute any of the other inst ruction setting. when the ic is in external clock operating mode, be sure to stop the external clock input after the lapse of the instruction execution time (27 s: f ck =300khz). ? display shift ... (display shift) code d56 d57 d58 d59 d60 d61 d62 d63 m a r/l x 0 0 1 1 x: don?t care m, a: specifies the data to be shifted m a shift operating state 0 0 neither mdata nor adata is shifted 0 1 only adata is shifted 1 0 only mdata is shifted 1 1 both mdata and adata are shifted r/l: specifies the shift direction r/l shift direction 0 shift left 1 shift right
LC75818PT no.a0964-15/43 ? set ac address... (set ac) code d48 d49 d50 d51 d52 d53 d54 d55 d56 d57 d58 d59 d60 d61 d62 d63 da0 da1 da2 da3 da4 da5 x x ra0 ra1 ra2 ra3 0 1 0 0 x: don?t care da0 to da5: dcram address da0 da1 da2 da3 da4 da5 lsb msb least significant bit mo st significant bit ra0 to ra3: adram address ra0 ra1 ra2 ra3 lsb msb least significant bit mo st significant bit this instruction loads the 6-bit dcram address da0 to da 5 and the 4-bit adram address ra0 to ra3 into the ac. ? dcram data write ... (write data to dcram) code d40 d41 d42 d43 d44 d45 d46 d47 d48 d49 d50 d51 d52 d53 d54 d55 d56 d57 d58 d59 d60 d61 d62 d63 ac0 ac1 ac2 ac3 ac4 ac5 ac6 ac7 da0 da1 da2 da3 da4 da5 x x im x x x 0 1 0 1 x: don?t care da0 to da5: dcram address da0 da1 da2 da3 da4 da5 lsb msb least significant bit mo st significant bit ac0 to ac7: dcram data (character code) ac0 ac1 ac2 ac3 ac4 ac5 ac6 ac7 lsb msb least significant bit mo st significant bit this instruction writes the 8 bits of data ac0 to ac7 to d cram. this data is a character code, and is converted to a 5 7, 5 8, or 5 9 dot matrix display data using cgrom or cgram. im: sets the method of writing data to dcram im dcram data write method 0 normal dcram data write (specifies the dcram address and writes the dcram data.) 1 increment mode dcram data write (increments the dcram address by +1 each time data is written to dcram.)
LC75818PT no.a0964-16/43 notes: *14. ? dcram data write method when im = 0 ? dcram data write method when im = 1 (instructions other than the ?dcram data write? instruction cannot be executed.) data format at (1) (24 bits) code d40 d41 d42 d43 d44 d45 d46 d47 d48 d49 d50 d51 d52 d53 d54 d55 d56 d57 d58 d59 d60 d61 d62 d63 ac0 ac1 ac2 ac3 ac4 ac5 ac 6 ac7 da0 da1 da2 da3 da4 da5 x x im x x x 0 1 0 1 x: don?t care data format at (2) (8 bits) code d56 d57 d58 d59 d60 d61 d62 d63 ac0 ac1 ac2 ac3 ac4 ac5 ac6 ac7 data format at (3) (16 bits) code d48 d49 d50 d51 d52 d 53 d54 d55 d56 d57 d58 d59 d60 d61 d62 d63 ac0 ac1 ac2 ac3 ac4 ac5 ac 6 ac7 0 x x x 0 1 0 1 x: don?t care ? adram data write ... (write data to adram) code d40 d41 d42 d43 d44 d45 d46 d47 d48 d49 d50 d51 d52 d53 d54 d55 d56 d57 d58 d59 d60 d61 d62 d63 ad1 ad2 ad3 ad4 ad5 x x x ra0 ra1 ra2 ra3 x x x x im x x x 0 1 1 0 x: don?t care ra0 to ra3:adram address ra0 ra1 ra2 ra3 lsb msb least significant bit most significant bit dcram data write finishes dcram data write finishes dcram data write finishes dcram data write finishes instruction execution time (1) (1) (1) ccb address ccb address ccb address ccb address 24 bit 24 bit 24 bit (1) ce di dcram 24 bit instruction execution time instruction execution time instruction execution time ccb address 8 bit instruction execution time ccb address 8 bit ccb address 8 bit ccb address 8 bit ccb address ccb address dcram data write finishes (3) (2) (2) (2) (2) (1) di dcram ce instructions other than the ?dcram data write? instruction cannot be executed. 24 bit 16 bit instruction execution time instruction execution time instruction execution time instruction execution time instruction execution time dcram data write finishes dcram data write finishes dcram data write finishes dcram data write finishes dcram data write finishes
LC75818PT no.a0964-17/43 ad1 to ad5: adata display data in addition to the 5 7, 5 8, or 5 9 dot matrix display data (mdata), this ic supports direct display of the five accessory display segments provided in ea ch digit as adata. this display f unction does not use cgrom or cgram. the figure below shows the corresponden ce between the data and the display. when adn = 1(where n is an integer between 1 and 5) the segment corresponding to that data will be turned on. adata corresponding output pin ad1 ad2 ad3 ad4 ad5 s5m+1 (m is an integer between 0 and 15) s5m+2 s5m+3 s5m+4 s5m+5 im: sets the method of writing data to adram im adram data write method 0 normal adram data write (specifies the adram address and writes the adram data.) 1 increment mode adram data write (inc rements the adram address by +1 each time data is written to adram.) notes: *15. ? adram data write method when im = 0 ? adram data write method when im = 1 (instructions other than the ?adram data write? instruction cannot be executed.) adram data write finishes adram data write finishes adram data write finishes adram data write finishes instruction execution time (4) (4) (4) ccb address ccb address ccb address ccb address 24 bit 24 bit 24 bit (4) ce di adram 24 bit instruction execution time instruction execution time instruction execution time 16 bit ccb address ccb address 8 bit 8 bit ccb address 8 bit 8 bit ccb address ccb address ccb address adram data write finishes (6) (5) (5) (5) (5) (4) di adram ce instructions other than the ?adram data write? instruction cannot be executed. 24 bit instruction execution time instruction execution time instruction execution time instruction execution time instruction execution time instruction execution time adram data write finishes adram data write finishes adram data write finishes adram data write finishes adram data write finishes s5m+1 s5m+5 (m is an integer between 0 and 15)
LC75818PT no.a0964-18/43 data format at (4) (24 bits) code d40 d41 d42 d43 d44 d45 d46 d47 d48 d49 d50 d51 d52 d53 d54 d55 d56 d57 d58 d59 d60 d61 d62 d63 ad1 ad2 ad3 ad4 ad5 x x x ra0 ra1 ra2 ra3 x x x x im x x x 0 1 1 0 x: don?t care data format at (5) (8 bits) code d56 d57 d58 d59 d60 d61 d62 d63 ad1 ad2 ad3 ad4 ad5 x x x x: don?t care data format at (6) (16 bits) code d48 d49 d50 d51 d52 d 53 d54 d55 d56 d57 d58 d59 d60 d61 d62 d63 ad1 ad2 ad3 ad4 ad5 x x x 0 x x x 0 1 1 0 x: don?t care ? cgram data write ... (write data to cgram) code d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 cd1 cd2 cd3 cd4 cd5 cd6 cd7 cd8 cd9 cd10 cd11 cd12 cd13 cd14 cd15 cd16 code d16 d17 d18 d19 d20 d 21 d22 d23 d24 d25 d26 d27 d28 d29 d30 d31 cd17 cd18 cd19 cd20 cd21 cd22 cd23 cd24 cd25 cd26 cd27 cd28 cd29 cd30 cd31 cd32 code d32 d33 d34 d35 d36 d 37 d38 d39 d40 d41 d42 d43 d44 d45 d46 d47 cd33 cd34 cd35 cd36 cd37 cd38 cd39 cd 40 cd41 cd42 cd43 cd44 cd45 x x x code d48 d49 d50 d51 d52 d 53 d54 d55 d56 d57 d58 d59 d60 d61 d62 d63 ca0 ca1 ca2 ca3 ca4 ca5 ca6 ca7 x x x x 0 1 1 1 x: don?t care ca0 to ca7: cgram address ca0 ca1 ca2 ca3 ca4 ca5 ca6 ca7 lsb msb least significant bit mo st significant bit cd1 to cd45: cgram data (5 7, 5 8, or 5 9 dot matrix display data) the bit cdn (where n is an integer between 1 and 45) corresponds to the 5 7, 5 8, or 5 9 dot matrix display data. the figure below shows that correspondence. when cdn is 1 the dots which correspond to that data will be turned on. cd1 cd2 cd3 cd4 cd5 cd6 cd7 cd8 cd9 cd10 cd11 cd12 cd13 cd14 cd15 cd16 cd17 cd18 cd19 cd20 cd21 cd22 cd23 cd24 cd25 cd26 cd27 cd28 cd29 cd30 cd31 cd32 cd33 cd34 cd35 cd36 cd37 cd38 cd39 cd40 cd41 cd42 cd43 cd44 cd45 note: *16. cd1 to cd35: 5 7 dot matrix display data cd1 to cd40: 5 8 dot matrix display data cd1 to cd45: 5 9 dot matrix display data
LC75818PT no.a0964-19/43 ? set display contrast? (set display contrast) code d48 d49 d50 d51 d52 d 53 d54 d55 d56 d57 d58 d59 d60 d61 d62 d63 ct0 ct1 ct2 ct3 x x x x ctc x x x 1 0 0 0 x: don?t care ct0 to ct3: sets the display contrast (11 steps) ct0 ct1 ct2 ct3 lcd drive 4/4 bias voltage supply v lcd 0 level 0 0 0 0 0.94v lcd =v lcd -(0.03v lcd 2) 1 0 0 0 0.91v lcd =v lcd -(0.03v lcd 3) 0 1 0 0 0.88v lcd =v lcd -(0.03v lcd 4) 1 1 0 0 0.85v lcd =v lcd -(0.03v lcd 5) 0 0 1 0 0.82v lcd =v lcd -(0.03v lcd 6) 1 0 1 0 0.79v lcd =v lcd -(0.03v lcd 7) 0 1 1 0 0.76v lcd =v lcd -(0.03v lcd 8) 1 1 1 0 0.73v lcd =v lcd -(0.03v lcd 9) 0 0 0 1 0.70v lcd =v lcd -(0.03v lcd 10) 1 0 0 1 0.67v lcd =v lcd -(0.03v lcd 11) 0 1 0 1 0.64v lcd =v lcd -(0.03v lcd 12) ctc: sets the display contrast adjustment circuit state ctc display contrast adjustment circuit state 0 the display contrast adjustment circuit is disabled, and the v lcd 0 pin level is forced to the v lcd level. 1 the display contrast adjustment circuit operat es, and the display contrast is adjusted. note that although the display contrast can be adjusted by op erating the built-in display contrast adjustment circuit, it is also possible to apply fine adjustments to the contrast by connecting an external variable resistor to the v lcd 4 pin and modifying the v lcd 4 pin voltage. however, the following conditions must be met: v lcd 0-v lcd 4 4.5v, and 1.5v v lcd 4 0v. ? set key scan output port/general-purpose output port state ... (key scan output port and general-purpose output port control) code d48 d49 d50 d51 d52 d 53 d54 d55 d56 d57 d58 d59 d60 d61 d62 d63 kc1 kc2 kc3 kc4 kc5 kc6 pc40 pc41 pc1 pc2 pc3 x 1 0 0 1 x:don?t care kc1 to kc6: sets the key scan output pin ks1 to ks6 state output pin ks1 ks2 ks3 ks4 ks5 ks6 key scan output state setting da ta kc1 kc2 kc3 kc4 kc5 kc6 when kc1 to kc3 are set to 1 and kc4 to kc6 are set to 0, in the key scan standby state, the ks1 to ks3 output pins will output the high level (v dd ) and ks4 to ks6 will output the low level (v ss ). note that key scan output signals are not output from output pins that are set to the low level. pc1, pc2, pc3: sets the general-purpose output port p1, p2, p3 state output pin p1 p2 p3 general-purpose output port state setting pc1 pc2 pc3 when pc1 is set to 1 and pc2 to pc3 are set to 0, p1 output pin will output the high levels (v dd ) and p2 to p3 will output the low levels (v ss ).
LC75818PT no.a0964-20/43 pc40, pc41: sets the general-purpose output port p4 state pc40 pc41 output pin (p4) state 0 0 ?l?(v ss ) 1 0 ?h?(v dd ) 0 1 clock signal output (fosc/2, f ck /2) 1 1 clock signal output (fosc/8, f ck /8) serial data output (1) when cl is stopped at the low level (2) when cl is stopped at the high level ? b0 to b3, a0 to a3: ccb address 43h ? kd1 to kd30: key data ? sa: sleep acknowledge data note: *17. if a key data read operation is executed when do is high, the read key data (kd1 to kd30) and sleep acknowledge data(sa) will be invalid. output data (1) kd1 to kd30: key data when a key matrix of up to 30 keys is formed from the ks1 to ks6 output pins and the ki1 to ki5 input pins and one of those keys is pressed, the key output data corresponding to that key will be set to 1. the table shows the relationship between those pins and the key data bits. ki1 ki2 ki3 ki4 ki5 ks1 kd1 kd2 kd3 kd4 kd5 ks2 kd6 kd7 kd8 kd9 kd10 ks3 kd11 kd12 kd13 kd14 kd15 ks4 kd16 kd17 kd18 kd19 kd20 ks5 kd21 kd22 kd23 kd24 kd25 ks6 kd26 kd27 kd28 kd29 kd30 (2) sa : sleep acknowledge data this output data bit is set to the state when the key was pr essed. also, while do will be low in this case, if serial data is input and the mode is set (to normal or sleep mode) during this period, that mode will be set. sa will be 1 in sleep mode and 0 in normal mode. x: don?t care ce a3 a2 a1 a0 b3 b2 b1 b0 kd2 kd1 x sa kd30 kd29 kd28 kd27 0 1 0 0 0 0 1 1 do di cl output data x: don?t care output data ce a3 a2 a1 a0 b3 b2 b1 b0 kd3 kd2 kd1 xx sa kd30 kd29 kd28 0 1 0 0 0 0 1 1 do di cl
LC75818PT no.a0964-21/43 key scan operation functions (1) key scan timing the key scan period is 2304t(s). to reliably determine the on/off state of the keys, the LC75818PT scans the keys twice and determines that a key has been pressed when the key data agrees. it outputs a key data read request (a low level on do) 4800t(s) after starting a key scan. if the key da ta dose not agree and a key was pressed at that point, it scans the keys again. thus the LC75818PT cannot detect a key press shorter than 4800t(s). note: *18. not that the high/low states of these pins are determined by the "set key scan output port/general-purpose output port state" instruction, and that key scan output signals are not output from pins that are set to low. (2) in normal mode ? the pins ks1 to ks6 are set to high or low with the "set key scan output port/general-purpose output port state" instruction. ? if a key on one of the lines corresponding to a ks1 to ks6 pin which is set high is pressed, a key scan is started and the keys are scanned until all keys are released. mu ltiple key presses are recognized by determining whether multiple key data bits are set. ? if a key is pressed for longer than 4800t(s) (where t=1/fosc, t=1/f ck ) the LC75818PT outputs a key data read request (a low level on do) to the controller. the controller acknowledges this request and reads the key data. however, if ce is high during a serial data transfer, do will be set high. ? after the controller reads the key data, the key data read request is cleared (do is set high) and the LC75818PT performs another key scan. also note that do, being an open-drain output, requires a pull-up resistor (between 1k and 10k ). key on 4608t[s] *18 *18 *18 *18 *18 *18 *18 *18 *18 *18 *18 1 1 2 2 3 3 4 4 5 5 6 6 ks4 ks5 ks6 ks3 ks2 *18 ks1 t= 1 fosc t= 1 f ck key address key scan t= t= key data read request key data read do di serial data transfer key address (43h) key address serial data transfer serial data transfer ce key input 2 key input 1 4800t[s] 4800t[s] 4800t[s] 1 fosc key data read request key data read request key data read key data read 1 f ck
LC75818PT no.a0964-22/43 (3) in sleep mode ? the pins ks1 to ks6 are set to high or low with the "set key scan output port/general-purpose output port state" instruction. ? if a key on one of the lines corresponding to a ks1 to ks6 pin which is set high is pressed in the rc oscillator operating mode, the oscillator on the osc pin is started (the ic starts receiving the extern al clock in external clock operating mode) and a key scan is performed . keys are scanned until all keys released. multiple key presses are recognized by determining whether multiple key data bits are set. ? if a key is pressed for longer than 4800t(s) (where t=1/fosc, t=1/f ck ) the LC75818PT outputs a key data read request (a low level on do) to the controller. the controller acknowledges this request and reads the key data. however, if ce is high during a serial data transfer, do will be set high. ? after the controller reads the key data, the key data read request is cleared (do is set high) and the LC75818PT performs another key scan. however, this dose not clear sleep mode. also note that do, being an open-drain output, requires a pull-up resistor (between 1k and 10k ). ? sleep mode key scan example example: when a "display on/off cont rol (sp=1)" instruction and a "set ke y scan output por t/general-purpose output port state (kc1 to kc5= 0, kc6=1)" instruction are executed. (i.e. sleep mode with only ks6 high.) note: *19. these diodes are required to reliably recognize multiple key presses on the ks6 line when sleep mode state with only ks6 high, as in the above example. that is, these diodes prevent incorrect operations due to sneak currents in the ks6 key scan output signal when keys on the ks1 to ks5 lines are pressed at the same time. multiple key presses although the LC75818PT is capable of key scanning without inserting diodes for dual key presses, triple key presses on the ki1 to ki5 input pin lines, or multiple key presses on the ks1 to ks6 output pin lines, multiple presses other than these cases may result in keys that were not pressed recognized as having been pressed. therefore, a diode must be inserted in series with each key. app lications that do not recognize multiple key presses of three or more keys should check the key data for three or more 1 bits and ignore such data. ki1 ki2 ki3 ki4 ki5 *19 ?l? ks3 ?h? ks6 ?l? ks2 when any one of these keys is pressed in rc oscillator operating mode, the oscillator on the osc pin is started (the ic starts receiving the external clock in external clock operating mode) and the keys are scanned. ?l? ks1 ?l? ks4 ?l? ks5 key address serial data transfer serial data transfer key data read request key data read do di key address (43h) serial data transfer ce key scan key input (ks6 line) 4800t[s] 4800t[s] t= 1 fosc key data read request key data read t= 1 f ck
LC75818PT no.a0964-23/43 1/8 duty, 1/4 bias drive technique when a "set display technique" instruction with fc = 0 is executed: f8 = , f8 = when a "set display technique" instruction with fc = 1 is executed: f8 = , f8 = fosc 3072 fosc 1536 f ck 3072 f ck 1536 v lcd 3 v lcd 4 v lcd 4 v lcd 2 v lcd 1 v lcd 0 v lcd 4 v lcd 3 v lcd 3 v lcd 2 v lcd 2 v lcd 1 v lcd 1 v lcd 0 v lcd 0 com8 com2 com1 lcd driver output when only lcd segments corresponding to com2 are turned on lcd driver output when only lcd segments corresponding to com1 are turned on v lcd 4 v lcd 3 v lcd 2 v lcd 1 v lcd 0 v lcd 4 v lcd 3 v lcd 2 v lcd 1 v lcd 0 v lcd 4 v lcd 3 v lcd 2 v lcd 0 t8 t8 8 v lcd 4 v lcd 3 v lcd 2 v lcd 1 v lcd 0 1 f8 t8= v lcd 1 lcd driver output when all lcd segments corresponding to com1 to com8 are turned off lcd driver output when all lcd segments corresponding to com1 to com8 are turned on
LC75818PT no.a0964-24/43 1/9 duty, 1/4 bias drive technique v lcd 3 v lcd 4 v lcd 4 v lcd 2 v lcd 1 v lcd 0 v lcd 4 v lcd 3 v lcd 3 v lcd 2 v lcd 2 v lcd 1 v lcd 1 v lcd 0 v lcd 0 com9 com2 com1 v lcd 4 v lcd 3 v lcd 2 v lcd 1 v lcd 0 v lcd 4 v lcd 3 v lcd 2 v lcd 1 v lcd 0 v lcd 4 v lcd 3 vlcd2 v lcd 1 v lcd 0 v lcd 4 v lcd 3 v lcd 2 v lcd 1 v lcd 0 t9 t9 9 1 f9 t9= when a "set display technique" instruction with fc = 0 is executed: f9 = , f9 = when a "set display technique" instruction with fc = 1 is executed: f9 = ,f9 = fosc 3456 fosc 1728 f ck 3456 f ck 1728 lcd driver output when only lcd segments corresponding to com2 are turned on lcd driver output when only lcd segments corresponding to com1 are turned on lcd driver output when all lcd segments corresponding to com1 to com9 are turned off lcd driver output when all lcd segments corresponding to com1 to com9 are turned on
LC75818PT no.a0964-25/43 1/10 duty, 1/4 bias drive technique 1 f10 v lcd 3 v lcd 4 v lcd 4 v lcd 2 v lcd 1 v lcd 0 v lcd 4 v lcd 3 v lcd 3 v lcd 2 v lcd 2 v lcd 1 v lcd 1 v lcd 0 v lcd 0 com10 com2 com1 v lcd 4 v lcd 3 v lcd 2 v lcd 1 v lcd 0 v lcd 4 v lcd 3 v lcd 2 v lcd 1 v lcd 0 v lcd 4 v lcd 3 v lcd2 v lcd 1 v lcd 0 v lcd 4 v lcd 3 v lcd 2 v lcd 1 v lcd 0 t10 t10 10 t10= when a "set display technique" instruction with fc = 0 is executed: f10 = , f10 = when a "set display technique" instruction with fc = 1 is executed: f10 = , f10 = fosc 3840 fosc 1920 f ck 3840 f ck 1920 lcd driver output when only lcd segments corresponding to com2 are turned on lcd driver output when only lcd segments corresponding to com1 are turned on lcd driver output when all lcd segments corresponding to com1 to com10 are turned off lcd driver output when all lcd segments corresponding to com1 to com10 are turned on
LC75818PT no.a0964-26/43 clock signal output waveform "set key scan output port/ general-purpose port state" instruction data pc40 pc41 general-purpose port p4 clock signal frequency fc (1/tc) [hz] 0 1 clock signal output (fosc/2, f ck /2) 1 1 clock signal output (fosc/8, f ck /8) voltage detection type reset circuit (v det ) this circuit generates an output signal and resets the sy stem when logic block power is first applied and when the voltage drops, i.e., when the logic block power supply voltage is less than or equal to the power down detection voltage v det ,which is 2.2v, typical. to assure that this function operates reliably, a capacitor must be added to the logic block power supply line so that the logic block power supply voltage v dd rise time when the logic block power is first applied and the logic block power supply voltage v dd fall time when the voltage drops are both at least 1ms. (see figure 5.) power supply sequence the following sequences must be observed when power is turned on and off. (see figure 5.) ? power on: logic block power supply(v dd ) on lcd driver block power supply (v lcd ) on ? power off: lcd driver block power supply(v lcd ) off logic block power supply (v dd ) off when 5v signal is applied to the ce, cl, di, and inh pins which are to be connected to the controller and if the logic block power supply (v dd ) is off, set the input voltage at the ce, cl , di, and inh pins to 0v and apply the 5v signal to these pins after turning on the logic block power supply (v dd ). system reset 1. reset function the LC75818PT performs a system reset with the v det . when a system reset is applied, the display is turned off, key scanning is disabled, the key data is reset, and the general-purpose output ports are set to and held at the low level (v ss ). these states that are created as a result of the system rese t can be cleared by executing the instruction described below. (see figure 5.) ? clearing the display off state display operation can be enabled by executing a ?display on/off control? instruction. however, since the contents of the dcram, adram, and cgram are undefined, applications must set the contents of these memories before turning on display with the ?display on/off control? instruction. that is, applications must execute the following instructions. ? set display technique (the "set display technique" instruction must be executed first.) ? dcram data write ? adram data write (if the adram is used.) ? cgram data write (if the cgram is used.) ? set ac address ? set display contrast (if the display contrast adjustment circuit is used.) after executing the above instructions, applications must turn on the display with a ?display on/off control? instruction. note that when applications turn off in the normal mode, applications must turn off the display with a ?display on/off control? instruction or the inh pin. p4 tc tc/2 1 fc tc=
LC75818PT no.a0964-27/43 ? clearing the key scan disable and key data reset states by executing the following instructions no t only create a state in which key scanni ng can be performed, but also clear the key data reset. ? "set display technique" (the "set display technique" instruction must be executed first.) ? "set key scan output port / general-purpose output port state" ? clearing the general-purpose output ports locked at the low level (v ss ) state by executing the following instructions clear the gene ral-purpose output ports locked at the low level (v ss ) state and set the states of the general-purpose output ports. ? "set display technique" (the "set display technique" instruction must be executed first.) ? "set key scan output port / general-purpose output port state" [figure 5] ? t1 1 [ms] (logic block power supply voltage v dd rise time) ? t2 0 ? t3 0 ? t4 1 [ms] (logic block power supply voltage v dd fall time) ? initial state settings set display technique (the "set display technique" instruction must be executed first.) dcram data write adram data write (if the adram is used.) cgram data write (if the cgram is used.) set ac address set display contrast (if the display contrast adjustment circuit is used.) "set display technique" and ?set key scan output port/ general-purpose output port state ? instruction execution ?display on/off control? instruction execution (turning the display on) ?display on/off control? instruction execution (turning the display off) v det v det t3 t4 t1 t2 key scan display state instruction execution v dd v lcd initial state settings display off display on can be set to such states as high (v dd ), or low (v ss ) level fixed at the low level (v ss ) display off execution enabled disabled general-purpose output ports
LC75818PT no.a0964-28/43 2. block states during a system reset (1) clock generator,timing generator when a reset is applied, these circuits are forcibly in itialized internally. then, when the "set display technique" instruction is executed, oscillation of th e osc pin starts in rc oscillator opera ting mode (the ic starts receiving the external clock in external clock operating mode), execution of the instruction is enabled. (2) instruction register, instruction decoder when a reset is applied, these circuits are forcibly initia lized internally. then, when instruction execution starts, the ic operates according to those instructions. (3) address register, address counter when a reset is applied, these circuits are forcibly initialized internally. then, the dcram and the adram addresses are set when ?set ac ad dress? instruction is executed. (4) dcram, adram, cgram since the contents of the dcram, adram, and cgram b ecome undefined during a reset, applications must execute ?dcram data write?, ?adram data write (if th e adram is used.)?, and ?c gram data write (if the cgram is used.)? instructions before executing a ?display on/off control? instruction. (5) cgrom character patterns are st ored in this rom. (6) latch although the value of the data in the latch is undefi ned during a reset, the adram, cgrom, and cgram data is stored by executing a ?display on/off control? instruction. (7) common driver, segment driver these circuits are forced to the displa y off state when a reset is applied. (8) contrast adjuster display contrast adjustment circuit oper ation is disabled when a reset is applied. after that, the display contrast can be set by executing a ?set display contrast? instruction. (9) key scan, key buffer when a reset is applied, these circuits are forcibly initia lized internally, and key scan operation is disabled. also, the key data is all set to 0. after that, key scanning can be performed by executing a "set key scan output port/general-purpose output port state" instruction. (10) general port when a reset is applied, the general-purpose output port state is locked at the low level (v ss ). (11) ccb interface, shift register these circuits go to the serial data input wait state.
LC75818PT no.a0964-29/43 (3) output pin states during the reset period output pin state during reset s1 to s80 com1 to com10 ks1 to ks6 p1 to p4 d0 l (v lcd 4) l (v lcd 4) l (v ss ) l (v ss ) h *20 note: *20. since this output pin is an open-drain output, a pull-up resistor (between 1k and 10k ) is required. this pin is held at the high level even if a key data read operation is performed before executing the "set display technique" or "set key scan output port/general-purpose output port state" instruction. s80 s79 inh adram 80 bits cgram 5 9 16 bits vdet clock generator contrast adjuster timing generator address register instruction register common driver instruction decoder address counter dcram 64 8 bits cgrom 5 9 240 bits s h i f t r e g i s t e r l a t c h s e g m e n t d r i v e r osc do di ks1 ks2 ks3 ks4 ks5 ks6 ce ki1 ki2 ki3 ki4 ki5 cl s1 s78 com10 com1 key buffer ccb interface key scan v dd v lcd 4 v lcd 3 v lcd 2 v lcd 1 v lcd v lcd 0 v ss test blocks that are reset general port p2 p1 p4 p3
LC75818PT no.a0964-30/43 osc pin peripheral circuit (1) rc oscillator operating mode (when the "set display technique (oc=0)" instruction is executed) when rc oscillator operating mode is selected, an external resistor rosc and an external capacitor cosc must be connected between the osc pin and gnd. (2) external clock operating mode (when the "set display technique (oc=1)" instruction is executed) when selecting the external clock operating mode, connect a current protection resistor rg (2.2 to 22k ) between the osc pin and external clock output pin (external oscillato r). determine the value of the resistance according to the maximum allowable current value at the external clock output pin. also make sure that the waveform of the external clock is not heavily distorted. note: *21. allowable current value at external clock output pin > note when applying a 5v signal to the ce, cl, di, and inh pins when applying a 5v signal to the ce, cl, di, and inh pins which are to be connected to the controller, set the input voltage to the ce, cl, di, and inh pins to 0v if the logic block power supply (v dd ) is off, and apply the 5v signal to those pins after turning on the logic block power supply (v dd ). osc cosc rosc osc external clock output pin rg external oscillator v dd rg
LC75818PT no.a0964-31/43 sample application circuit 1 1/8 duty, 1/4 bias drive technique (for use with normal panels) note * 22. add a capacitor to the logic block power supply line so that the logic block power supply voltage v dd rise time when power is applied and the logic block power supply voltage v dd fall time when power drops are both at least 1 ms, as the LC75818PT is reset by the v det . * 23. if a variable resistor is not used for display contrast fine adjustment, the v lcd 4 pin must be connected to ground. *24. in rc oscillator operating mode, an external resistor, rosc, and an external capacitor, cosc, must be connected between the osc pin and ground. when sel ecting the external clock operating mode, connect a current protection resistor rg (2.2 to 22k ) between the osc pin and the external clock output pin (external oscillator). (see the ?osc pin peripheral circuit? section.) *25. if the function of inh pin is not used, the inh pin must be connected to the logic block power supply v dd . *26. the do pin, being an open-drain output, requires a pull-up resistor. select a resistance (between 1k and 10k ) appropriate for the capacitance of the external wi ring so that signal wave forms are not degraded. *27 when applying a 5v signal to the ce, cl, di, and inh pins, set the input voltage to 0v if the logic block power supply (v dd ) is off, and apply the 5v signal to those pins after turning on the logic block power supply (v dd ). to the controller power supply to the controller from the controller lcd panel com8 com7 com6 com5 com4 com3 com2 com1 c c c c 0.047 f +8v *22 +3.3v inh *25 ce cl *26 do di osc *24 v lcd 4 *23 v lcd 3 v lcd 2 v lcd 1 open v lcd v lcd 0 v ss test v dd s80 s79 s78 s77 s76 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 general-purpose output ports used with the backlight controller or other circuit k i 5 key matrix (up to 30 keys) k i 4 k i 3 k i 2 k i 1 k s 6 k s 5 k s 4 k s 3 k s 2 k s 1 *27 p1 p2 p3 p4
LC75818PT no.a0964-32/43 sample application circuit 2 1/8 duty, 1/4 bias drive technique (for use with large panels) note * 22. add a capacitor to the logic block power supply line so that the logic block power supply voltage v dd rise time when power is applied and the logic block power supply voltage v dd fall time when power drops are both at least 1 ms, as the LC75818PT is reset by the v det . * 23. if a variable resistor is not used for display contrast fine adjustment, the v lcd 4 pin must be connected to ground. *24. in rc oscillator operating mode, an external resistor, rosc, and an external capacitor, cosc, must be connected between the osc pin and ground. when sel ecting the external clock operating mode, connect a current protection resistor rg (2.2 to 22k ) between the osc pin and the external clock output pin (external oscillator). (see the ?osc pin peripheral circuit? section.) *25. if the function of inh pin is not used, the inh pin must be connected to the logic block power supply v dd . *26. the do pin, being an open-drain output, requires a pull-up resistor. select a resistance (between 1k and 10k ) appropriate for the capacitance of the external wi ring so that signal wave forms are not degraded. *27 when applying a 5v signal to the ce, cl, di, and inh pins, set the input voltage to 0v if the logic block power supply (v dd ) is off, and apply the 5v signal to those pins after turning on the logic block power supply (v dd ). to the controller power supply to the controller from the controller lcd panel com8 com7 com6 com5 com4 com3 com2 com1 r r r r c c c c 0.047 ? r 2.2k +8v *22 +3.3v inh *25 ce cl *26 do di v lcd 4 *23 v lcd 3 v lcd 2 v lcd 1 v lcd v lcd 0 v ss test v dd s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 k s 1 k s 2 k s 3 k s 4 k s 5 k s 6 k i 1 k i 2 k i 3 k i 4 k i 5 key matrix (up to 30 keys) osc *24 s80 s79 s78 s77 s76 p1 p2 p3 p4 *27 general-purpose output ports used with the backlight controller or other circuit
LC75818PT no.a0964-33/43 sample application circuit 3 1/9 duty, 1/4 bias drive technique (for use with normal panels) note * 22. add a capacitor to the logic block power supply line so that the logic block power supply voltage v dd rise time when power is applied and the logic block power supply voltage v dd fall time when power drops are both at least 1 ms, as the LC75818PT is reset by the v det . * 23. if a variable resistor is not used for display contrast fine adjustment, the v lcd 4 pin must be connected to ground. *24. in rc oscillator operating mode, an external resistor, rosc, and an external capacitor, cosc, must be connected between the osc pin and ground. when sel ecting the external clock operating mode, connect a current protection resistor rg (2.2 to 22k ) between the osc pin and the external clock output pin (external oscillator). (see the ?osc pin peripheral circuit? section.) *25. if the function of inh pin is not used, the inh pin must be connected to the logic block power supply v dd . *26. the do pin, being an open-drain output, requires a pull-up resistor. select a resistance (between 1k and 10k ) appropriate for the capacitance of the external wi ring so that signal wave forms are not degraded. *27 when applying a 5v signal to the ce, cl, di, and inh pins, set the input voltage to 0v if the logic block power supply (v dd ) is off, and apply the 5v signal to those pins after turning on the logic block power supply (v dd ). to the controller power supply to the controller from the controller lcd panel com9 com8 com7 com6 com5 com4 com3 com2 com1 c c c c 0.047 f +8v *22 +3.3v inh *25 ce cl *26 do di v lcd 4 *23 v lcd 3 v lcd 2 v lcd 1 open v lcd v lcd 0 v ss test v dd s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 k s 1 k s 2 k s 3 k s 4 k s 5 k s 6 k i 1 k i 2 k i 3 k i 4 k i 5 key matrix (up to 30 keys) p1 p2 p3 p4 osc *24 s80 s79 s78 s77 s76 *27 general-purpose output ports used with the backlight controller or other circuit
LC75818PT no.a0964-34/43 sample application circuit 4 1/9 duty, 1/4 bias drive technique (for use with large panels) note * 22. add a capacitor to the logic block power supply line so that the logic block power supply voltage v dd rise time when power is applied and the logic block power supply voltage v dd fall time when power drops are both at least 1 ms, as the LC75818PT is reset by the v det . * 23. if a variable resistor is not used for display contrast fine adjustment, the v lcd 4 pin must be connected to ground. *24. in rc oscillator operating mode, an external resistor, rosc, and an external capacitor, cosc, must be connected between the osc pin and ground. when sel ecting the external clock operating mode, connect a current protection resistor rg (2.2 to 22k ) between the osc pin and the external clock output pin (external oscillator). (see the ?osc pin peripheral circuit? section.) *25. if the function of inh pin is not used, the inh pin must be connected to the logic block power supply v dd . *26. the do pin, being an open-drain output, requires a pull-up resistor. select a resistance (between 1k and 10k ) appropriate for the capacitance of the external wi ring so that signal wave forms are not degraded. *27 when applying a 5v signal to the ce, cl, di, and inh pins, set the input voltage to 0v if the logic block power supply (v dd ) is off, and apply the 5v signal to those pins after turning on the logic block power supply (v dd ). to the controller power supply to the controller from the controller lcd panel com9 com8 com7 com6 com5 com4 com3 com2 com1 r r r r c c c c 0.047 ? r 2.2k +8v *22 +3.3v inh *25 ce cl *26 do di v lcd 4 *23 v lcd 3 v lcd 2 v lcd 1 vlcd v lcd 0 v ss test v dd s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 k s 1 k s 2 k s 3 k s 4 k s 5 k s 6 k i 1 k i 2 k i 3 k i 4 k i 5 key matrix (up to 30 keys) p1 p2 p3 p4 osc *24 s80 s79 s78 s77 s76 *27 general-purpose output ports used with the backlight controller or other circuit
LC75818PT no.a0964-35/43 sample application circuit 5 1/10 duty, 1/4 bias drive technique (for use with normal panels) note * 22. add a capacitor to the logic block power supply line so that the logic block power supply voltage v dd rise time when power is applied and the logic block power supply voltage v dd fall time when power drops are both at least 1 ms, as the LC75818PT is reset by the v det . * 23. if a variable resistor is not used for display contrast fine adjustment, the v lcd 4 pin must be connected to ground. *24. in rc oscillator operating mode, an external resistor, rosc, and an external capacitor, cosc, must be connected between the osc pin and ground. when sel ecting the external clock operating mode, connect a current protection resistor rg (2.2 to 22k ) between the osc pin and the external clock output pin (external oscillator). (see the ?osc pin peripheral circuit? section.) *25. if the function of inh pin is not used, the inh pin must be connected to the logic block power supply v dd . *26. the do pin, being an open-drain output, requires a pull-up resistor. select a resistance (between 1k and 10k ) appropriate for the capacitance of the external wi ring so that signal wave forms are not degraded. *27 when applying a 5v signal to the ce, cl, di, and inh pins, set the input voltage to 0v if the logic block power supply (v dd ) is off, and apply the 5v signal to those pins after turning on the logic block power supply (v dd ). to the controller power supply to the controller from the controller lcd panel com10 com9 com8 com7 com6 com5 com4 com3 com2 com1 c c c c 0.047 f +8v *22 +3.3v inh *25 ce cl *26 do di v lcd 4 *23 v lcd 3 v lcd 2 v lcd 1 open vlcd v lcd 0 v ss test v dd s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 k s 1 k s 2 k s 3 k s 4 k s 5 k s 6 k i 1 k i 2 k i 3 k i 4 k i 5 key matrix (up to 30 keys) p1 p2 p3 p4 osc *24 s80 s79 s78 s77 s76 *27 general-purpose output ports used with the backlight controller or other circuit
LC75818PT no.a0964-36/43 sample application circuit 6 1/10 duty, 1/4 bias drive technique (for use with large panels) note * 22. add a capacitor to the logic block power supply line so that the logic block power supply voltage v dd rise time when power is applied and the logic block power supply voltage v dd fall time when power drops are both at least 1 ms, as the LC75818PT is reset by the v det . * 23. if a variable resistor is not used for display contrast fine adjustment, the v lcd 4 pin must be connected to ground. *24. in rc oscillator operating mode, an external resistor, rosc, and an external capacitor, cosc, must be connected between the osc pin and ground. when sel ecting the external clock operating mode, connect a current protection resistor rg (2.2 to 22k ) between the osc pin and the external clock output pin (external oscillator). (see the ?osc pin peripheral circuit? section.) *25. if the function of inh pin is not used, the inh pin must be connected to the logic block power supply v dd . *26. the do pin, being an open-drain output, requires a pull-up resistor. select a resistance (between 1k and 10k ) appropriate for the capacitance of the external wi ring so that signal wave forms are not degraded. *27 when applying a 5v signal to the ce, cl, di, and inh pins, set the input voltage to 0v if the logic block power supply (v dd ) is off, and apply the 5v signal to those pins after turning on the logic block power supply (v dd ). com10 to the controller power supply to the controller from the controller lcd panel com9 com8 com7 com6 com5 com4 com3 com2 com1 r r r r c c c c 0.047 ? r 2.2k +8v *22 +3.3v inh *25 ce cl *26 do di v lcd 4 *23 v lcd 3 v lcd 2 v lcd 1 v lcd v lcd 0 v ss test v dd s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 k s 1 k s 2 k s 3 k s 4 k s 5 k s 6 k i 1 k i 2 k i 3 k i 4 k i 5 key matrix (up to 30 keys) p1 p2 p3 p4 osc *24 s80 s79 s78 s77 s76 *27 general-purpose output ports used with the backlight controller or other circuit
LC75818PT no.a0964-37/43 sample correspondence between instructions and the display (when the LC75818PT-8560 is used) lsb instruction (hexadecimal) msb no. d40 to d43 d44 to d47 d48 to d51 d52 to d55 d56 to d59 d60 to d63 display operation 1 power application (initialization with the v det ) initializes the ic. the display is in the off state. set display technique 2 0 8 sets to 1/8 duty 1/4 bias display drive technique dcram data write (increment mode) 3 0 2 0 0 1 a writes the display data ? ? to dcram address 00h dcram data write (increment mode) 4 3 5 writes the display data ?s? to dcram address 01h dcram data write (increment mode) 5 1 4 writes the display data ?a? to dcram address 02h dcram data write (increment mode) 6 e 4 writes the display data ?n? to dcram address 03h dcram data write (increment mode) 7 9 5 writes the display data ?y? to dcram address 04h dcram data write (increment mode) 8 f 4 writes the display data ?o? to dcram address 05h dcram data write (increment mode) 9 0 2 writes the display data ? ? to dcram address 06h dcram data write (increment mode) 10 c 4 writes the display data ?l? to dcram address 07h dcram data write (increment mode) 11 3 5 writes the display data ?s? to dcram address 08h dcram data write (increment mode) 12 9 4 writes the display data ?i? to dcram address 09h dcram data write (increment mode) 13 0 2 writes the display data ? ? to dcram address 0ah dcram data write (increment mode) 14 c 4 writes the display data ?l? to dcram address 0bh dcram data write (increment mode) 15 3 4 writes the display data ?c? to dcram address 0ch dcram data write (increment mode) 16 7 3 writes the display data ?7? to dcram address 0dh dcram data write (increment mode) 17 5 3 writes the display data ?5? to dcram address 0eh dcram data write (increment mode) 18 8 3 writes the display data ?8? to dcram address 0fh dcram data write (increment mode) 19 1 3 writes the display data ?1? to dcram address 10h dcram data write (increment mode) 20 8 3 writes the display data ?8? to dcram address 11h dcram data write (increment mode) 21 0 2 0 a writes the display data ? ? to dcram address 12h continued on next page.
LC75818PT no.a0964-38/43 continued from preceding page. lsb instruction (hexadecimal) msb no. d40 to d43 d44 to d47 d48 to d51 d52 to d55 d56 to d59 d60 to d63 display operation set ac address 22 0 0 0 2 loads the dcram address 00h and the adram address 0h into ac display on/off control 23 f f f f 1 4 turns on the lcd for all digits (16 digits) in mdata display shift 24 1 c shifts the display (mdata only) to the left display shift 25 1 c shifts the display (mdata only) to the left display shift 26 1 c shifts the display (mdata only) to the left display shift 27 1 c shifts the display (mdata only) to the left display shift 28 1 c shifts the display (mdata only) to the left display shift 29 1 c shifts the display (mdata only) to the left display on/off control 30 0 0 0 0 8 4 set to sleep mode, turns off the lcd for all digits display on/off control 31 f f f f 1 4 turns on the lcd for all digits (16 digits) in mdata set ac address 32 0 0 0 2 loads the dcram address 00h and the adram address 0h into ac note: *28. this sample above assumes the use of 16 digits 5 7 dot matrix lcd. cgram and adram are not used. sanyo lsi lc758 sanyo lsi lc7581 anyo lsi lc75818 nyo lsi lc75818 yo lsi lc75818 o lsi lc75818 lsi lc75818 lsi lc75818 sanyo lsi lc758
LC75818PT no.a0964-39/43 notes on the controller key data read techniques 1. timer based key data acquisition ? flowchart ? timing chart t5: key scan execution time when the key data agreed for two key scans. (4800t(s)) t6: key scan execution time when the key data did not agree for two key scans and the key scan was executed again. (9600t(s)) t7: key address (4 3h) transfer time t8: key data read time ? explanation in this technique, the controller uses a timer to determ ine key on/off states and read the key data. the controller must check the do state when ce is low every t9 period without fail. if do is low, the controller recognizes that a key has been pressed and executes the key data read operation. the period t9 in this technique must satisfy the following condition. t9>t6+t7+t8 if a key data read operation is executed when do is high, the read key data (kd1 to kd30) and sleep acknowledge data (sa) will be invalid . key data read processing yes no do=?l? ce=?l? controller determination (key on) controller determination (key on) controller determination (key off) controller determination (key on) controller determination (key off) key data read request key data read do di ce key on key on key address key scan key input t6 t9 t9 t9 t9 t5 t8 t8 t7 t7 t5 t7 t8 t5 1 fosc t= 1 f ck t=
LC75818PT no.a0964-40/43 2. interrupt based key data acquisition ? flowchart ? timing chart t5: key scan execution time when the key data agreed for two key scans. (4800t(s)) t6: key scan execution time when the key data did not agree for two key scans and the key scan was executed again. (9600t(s)) t7: key address (4 3h) transfer time t8: key data read time key data read processing yes yes no do=?l? ce=?l? wait for at least t10 key off ce=?l? no do=?h? controller determination (key off) key on key on key scan controller determination (key on) controller determination (key off) controller determination (key on) controller determination (key on) controller determination (key on) key data read request key data read do di ce key address key input t10 t10 t10 t10 t5 t6 t8 t8 t7 t7 t5 t7 t8 t5 t7 t8 1 fosc t= 1 f ck t=
LC75818PT no.a0964-41/43 ? explanation in this technique, the controller uses interrupts to determine key on/off states and read the key data. the controller must check the do state when ce is low. if do is low, the controller recognizes that a key has been pressed and executes the key data read operation. after that the next key on/off determination is performed after the time t10 has elapsed by checking the do state when ce is low and reading the key data. the period t10 in this technique must satisfy the following condition. t10 > t6 if a key data read operation is executed when do is high, the read key data (kd1 to kd30) and sleep acknowledge data (sa) will be invalid.
LC75818PT no.a0964-42/43 LC75818PT-8560 character font (standard) ? a ? ? ? ? ? ? ? ? ? ? s s ? ? ? a n e ? a ? ? ? ? ? ? ? ? ? o n g i ij g i i j p q r s t u v w x y z a b c d e f g h i j k l m n o p q r s t u v w x y z [ _ ] 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0@ a b c d e f g h i j k l m n o 1 2 3 4 5 6 7 8 9 : ; < = > ? ! # $ % & ' ( ) * , . / cg ram(1) (16) (15) (14) (13) (12) (11) (10) (9) (8) (7) (6) (5) (4) (3) (2) 0 0 0 1 0 0 0 0 lsb 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 msb 0 0 0 0 upper 4bit lower 4bit
LC75818PT no.a0964-43/43 ps on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc). scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc mak es no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability ar ising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequentia l or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s techn ical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorize d for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other appli cation in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of persona l injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture o fthe part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws a nd is not for resale in any manner.

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